A voltage controlled oscillator (VCO) is an important component in many communication systems and radar systems. In general, a VCO receives an input control voltage (aka “tuning voltage”) and generates an output signal whose frequency changes in response to the control voltage. Any given VCO will have a frequency or tuning range defined by the minimum and maximum frequencies that are generated in response to the range of the control voltage which it is designed to receive. VCOs have been designed to operate in a variety of different frequency bands, including particularly VHF, UHF, and/or microwave frequency bands.
In many applications, the frequency accuracy and stability of a VCO operating in an “open loop” mode is unsatisfactory, because of component tolerances, production tolerances, variations in voltage levels, temperature drift, aging, etc. Accordingly, in many applications a VCO's output signal is frequency and/or phase locked to a more stable frequency source, such as a crystal oscillator, an acoustic resonator device, or the like.
A VCO can be phase locked to a reference oscillator by digital or analog phase lock techniques.
FIG. 1 illustrates one embodiment of a phase-locked loop (PLL). PLL 100 includes a reference oscillator 110 (e.g., a crystal oscillator), a reference frequency divider 120, a digital phase detector 130, a loop filter 140, a VCO 150, and feedback frequency divider 160. In operation, the VCO output frequency FVCO is divided by N to produce the feedback signal of frequency FVCO/N, while the reference frequency FREF is divided by M to produce a comparison signal of frequency FREF/M. The frequencies FVCO/N and FREF/M are compared by the digital phase detector 130 to produce a control signal which is filtered by loop filter 140 to produce the control voltage VCONTROL for tuning the frequency of VCO 150. Loop filter 140 may take a variety of forms, but it typically a single pole “RC” low pass filter, or a lag-lead filter.
When PLL 100 is locked, then FVCO/N=FREF/M, yielding:FVCO=(M/N)*FREF  (1)
So given a reference frequency FREF, by properly selecting divider values M and N one can select a desired output frequency FVCO. When the divider values M and N are programmable, then digital PLL 100 may operate as a PLL frequency synthesizer.
One important performance characteristic for a frequency source is the phase noise response of the VCO output signal, x(t). In the case of PLL 100, reference oscillator 110 and VCO 150 both contribute to the phase noise of the output signal. More specifically, the phase noise of the output signal at lower offset or modulation frequencies (e.g., frequencies within the bandwidth of loop filter 140) is controlled primarily by the phase noise of reference oscillator 110, and the phase noise of the output signal at higher offset or modulation frequencies (e.g., frequencies outside the bandwidth of loop filter 140) is controlled primarily by the phase noise of VCO 150.
PLL 100 is self-acquiring and can operate with VCO frequencies over a very wide range. The upper frequency limit of a digital PLL is set by the loop divider. Current high-speed dividers easily allow VCO frequencies up to 20 GHz. However, PLL 100 also has some disadvantages. First, the cost is sometimes uneconomical. Second, the combined noise floor of the feedback frequency divider 160, the reference divider 120, and the digital phase detector 130 can set a floor on the phase noise of the VCO output signal x(t).
FIG. 2 illustrates another embodiment of a phase-locked loop (PLL). PLL 200 includes a reference oscillator 210 (e.g., a crystal oscillator), a sampling phase detector (SPD) 230, a loop amplifier 240, and a VCO 250.
In operation SPD 230 receives the VCO output signal from VCO 250 at frequency FVCO, and the reference signal from reference oscillator 210 at frequency FREF. SPD 230 acts as a non-continuous phase detector that periodically samples the phase of the VCO output signal from VCO 250. The period of the sample pulse is 1/FREF, and the sample pulse directly samples the VCO output signal. Thus SPD 230 compares the phase of the two signals which are different in frequency, and outputs a beat signal or error signal Vbeat=Em sin Ø representing the differential phase error between the output signals of VCO 250 and reference oscillator 210. Loop amplifier 240 amplifies the error signal and provides the amplified error signal to VCO 250 to correct the VCO output signal to be in phase with the reference signal from reference oscillator 210. At the same time, loop amplifier 240 acts as a low pass filter and filters out the high frequency mixing products. As a result, the VCO output signal is frequency and phase locked to a harmonic of the reference frequency.
FIG. 3 is a schematic diagram of one embodiment of a sampling phase detector (SPD) 300. SPD 300 includes balancing transformer 310, module 320, and coupling circuit 330. Module 320 includes a step-recovery-diode (SRD) 322 which is connected in parallel with a pair of series-connected diodes (e.g., Schottky diodes) 324 by means of two equal-dimensioned coupling capacitors 326. In one embodiment, module 310 includes a ceramic substrate on which circuit elements 322, 324 and 326 are mounted in film circuit technology (thick or thin film technology). Example embodiments of module 320 include models SPD1101-111, SPD1102-111, and SPD1103-111 by SKYWORKS SOLUTIONS, INC., and the MSPD series SPDs from AEROFLEX/METELICS.
In operation, SRD 322 is controlled by a sampling signal (which in FIG. 2 corresponds to reference signal of frequency FREF). The sampling signal arrives at SRD 322 via balancing transformer 310. The terminals of SRD 322 are each connected electrically with an R/C network, and each terminal includes a parasitic inductance L not shown in FIG. 3.
SRD 322 operates by alternately producing and consuming a charge, based on the frequency of the sampling signal. Operation of SRD 322 will be explained with respect to FIG. 4 which illustrates the current through SRD 322 as a function of time in response to a sinusoidal sampling signal.
During a first portion of each sampling cycle of the sampling signal, SRD 322 is forward biased and conducts current as a “normal” diode while it builds up an internal charge. During a subsequent second portion of each sampling cycle of the sampling signal, SRD 322 is then reverse-biased. During the reverse-bias portion of the cycle, initially SRD 322 appears to act as a low impedance and maintains conduction by consuming the internal stored charge that was accumulated during the forward-bias portion of the sampling cycle. However when the stored charge has been fully consumed, the impedance of SRD 322 very quickly returns to its normal reverse impedance, which is very high. As a result, as shown in FIG. 4, SRD begins to “snap-off” at snap time TSNAP, and very quickly reverts to zero conduction during a transition time TT.
In SPD 300, SRD 322 depends upon on extremely fast transition time TT to generate pulses rich in harmonics. By storing charge during the positive-going half cycle of an input sinusoidal sampling signal and then “extracting” that charge during the negative-going half cycle, a voltage pulse with a rise time equivalent to transition time TT is generated. Accordingly, each time SRD 322 receives a charge during the “forward-bias” portion of the sampling cycle, a comparatively rapid discharge pulse occurs during the “reverse-bias” portion of the sampling cycle which is conducted by means of the coupling capacitors 326 to the diode pair 324.
The discharge pulse from SRD 322 connects the diode pair 324 (a diode arrangement comprising more than two diodes can be used instead of diode pair 324). The phase state of the VCO input signal applied to diode pair 324 from a VCO input 332 is detected by the switching operation of the diode pair 324. Coupling circuit 330 connected to diode pair 324 charges or discharges according to the phase shift between the VCO input signal and the sampling signal. A beat signal representing the above-described phase shift is provided at an IF output 334 of coupling circuit 330. Coupling circuit 330 decouples the beat signal supplied at IF output 334, from the VCO input signal received at VCO input 332.
Turning back to FIG. 2, noise contributions from the reference signal from reference oscillator 210, and loop components such as VCO 250 itself, SPD 230, and loop amplifier 240 can all add to the phase noise of VCO output signal. SPD 230 is typically the dominant noise contributor and thus improving its phase noise directly results in a corresponding improvement to the output noise of the VCO.
What is needed, therefore, is an arrangement for phase-locking a VCO to a reference signal where the VCO output signal's phase noise response is improved.